MU

Analyst DD (Substack)

• 7Substack · damnang·BULLISH / SUPPLY·10 days agopost

  The author contends the semiconductor selloff is driven by memory-cycle fears that assume 2028 oversupply, structural Chinese entry, and hyperscaler funding exhaustion all hit at once. He argues this is somewhat overdone because the market's capex-to-bits math fails to account for HBM, which lowers the number of bits produced per wafer and thus tempers the feared supply glut.

  Evidence

  • Micron fell 2.3% in New York overnight alongside ASML -5.8% and Nvidia -5.0%
  • Memory is a price-cycle industry; forecasts diverge on when profits at Samsung, SK hynix and Micron turn over
  • Market worry is that ~$75B of combined big-three capex lands as bits in 2028
  • 1GB of HBM3E consumed roughly the wafer area of 3GB of commodity DRAM; 16-high HBM4 pushed that to four times
  • SK hynix example: peak quarterly EPS 150,000 won annualizes to 600,000 won; today's price is 2.6x that, implying the market expects ~70% of peak earnings to disappear within four quarters
  Catalysts

  • SK hynix results released July 29 could settle the memory-cycle concern
  • CXMT Shanghai debut (+471%, passing Intel in market value) intensifying China-supply fears
  • Report of China developing immersion DUV lithography
  • Disclosure of Nvidia backstopping $250B of OpenAI data center investment reviving circular-financing concerns
  Risks

  • 2028 oversupply could be locked in if supply arrives all at once while AI demand stops
  • China's entry into memory/lithography could be structural
  • Hyperscalers may no longer be able to keep funding the AI buildout
  • Memory earnings could fall to roughly 30% of peak
• 7Substack · damnang·BULLISH / MOAT·30 days agopost

  The author disagrees with the bearish cyclical view on memory, arguing the commodity premise is breaking down as the HBM base die moves to a logic process (HBM4), gains customer-specific circuitry (cHBM), and eventually sits beneath the compute die (memory-on-logic). Micron, as one of the three memory makers, participates in this shift toward custom silicon partnerships that current bit-growth/ASP valuation models do not yet reflect.

  Evidence

  • Micron alone keeps the base die on its existing DRAM process through HBM4 on cost grounds and plans to move to a TSMC logic process from HBM4E
  • Samsung, SK hynix, and Micron have all placed custom HBM on their official roadmaps
  • A cHBM/memory carrying a customer's circuitry becomes a dedicated part that cannot easily be swapped for another supplier's product
  • A 2025 Georgia Tech / SK hynix paper modeled memory-on-logic at 64x the throughput and 3x the energy efficiency of 2.5D
  Catalysts

  • cHBM adoption already appearing on product roadmaps
  • Potential cHBM on NVIDIA's Feynman generation (2028)
  • Micron's planned move to a TSMC logic process from HBM4E
  Risks

  • The memory-on-logic heat problem (DRAM sensitivity and refresh under a hot compute die) remains unsolved
  • The cited throughput/efficiency figures are academic modeling and need not be taken at face value
  • The custom transition has never yet shown up in reported revenue/margin numbers
• 7Substack · damnang·BULLISH / SUPPLY·50 days agopost

  The author argues today's DRAM shortage is structural, not cyclical: HBM eats far more wafer capacity than standard DRAM, new fabs don't arrive until 2027 and get allocated to HBM first, and the three makers are deliberately withholding aggressive expansion. This locks in tight supply and pricing power for memory makers like Micron through 2028-2029.

  Evidence

  • By Micron's published numbers, HBM consumes wafer capacity against DDR5 at three to one
  • HBM goes from ~8% bit supply share in 2025 to ~13% in 2027, but on a wafer-start basis from 18% to 30%
  • Micron's Idaho fab does not come online until 2027
  • Q1 DRAM contract prices jumped 90-95% QoQ with a further 58-63% rise expected in Q2 (TrendForce)
  • DDR4 became more expensive than DDR5, a price inversion that cannot appear in a normal market
  • Samsung and SK hynix together hold ~70% of global DRAM and have signaled they will not grow capacity aggressively
  Catalysts

  • New lines at SK hynix Yongin, Samsung Pyeongtaek/Taylor and Micron Idaho ship first in 2027-2028, allocated to HBM first
  • Analyst consensus puts meaningful easing at 2H 2027 earliest, normalization 2028-2029
  Risks

  • Market reads the shortage as a cycle peak that ends when demand cools
  • Easing could come if AI investment bends
  • NAND is also tight now, with Q2 NAND contract prices up 70-75%
• 7Substack · damnang·NEUTRAL / DEMAND·61 days agopost

  NVIDIA is reportedly lowering the SOCAMM standard build from 192GB to 96GB modules, cutting CPU-side DRAM per rack from ~54TB to ~28TB, which dragged Micron down. The author argues this is not necessarily a demand collapse: SOCAMM bit demand is the product of module capacity, modules per system, and systems shipped, so a lower per-system content can be offset if loosened supply lets more systems install. HBM4 capacity holds while bandwidth nearly triples, and Micron is preparing the HBM4 hot lane and SOCAMM2 for Vera Rubin.

  Evidence

  • GB300 NVL72 put forward 20.7TB of HBM3e and 576TB/s; Vera Rubin NVL72 puts forward 20.7TB of HBM4 and 1,580TB/s of GPU memory bandwidth
  • SemiAnalysis reported standard build shifts from 192GB to 96GB modules, dropping CPU-side memory per rack from ~54TB to ~28TB
  • Rack cost falls from about $7.6M to $6.8M, lowering TCO per GPU
  • SOCAMM bit demand = module capacity x modules per system x systems shipped
  • Micron referenced HBM4 high-volume production and SOCAMM2 volume shipment for Vera Rubin together
  Catalysts

  • How many Vera Rubin systems actually get installed and in what configuration
  • HBM4 high-volume production ramp for Vera Rubin
  Risks

  • 96GB modules halve per-system SOCAMM content
  • LPDDR5X chip supply not keeping up with the full standard build
  • If system count does not make up for the per-system cut, memory demand could genuinely weaken
  • HBM4 capacity does not rise much over the prior generation
• 7Substack · damnang·BULLISH / EXECUTION·65 days agopost

  Micron, alongside Samsung and SK hynix, has invested in and is seriously evaluating MicroLED optical interconnect (Avicena's LightBundle) because its 'wide and slow' parallelization philosophy mirrors HBM's, and optics could free memory from package geometry constraints. The investment is framed as insurance on what comes after HBM rather than a near-term product plan.

  Evidence

  • Micron Ventures participated in Avicena's August 2022 $25M Series A alongside Samsung Catalyst Fund
  • All three memory makers (Samsung, SK hynix, Micron) are on Avicena's cap table
  • Per author's industry network, current employees at all three memory makers are very seriously evaluating MicroLED for memory optical interconnect
  • LightBundle's wide parallel-channel approach extends HBM's I/O philosophy (1024 pins, 2048 in HBM4) into the optical domain
  • Optical link with ~10m reach would liberate memory from CoWoS/reticle package limits
  Catalysts

  • Avicena eKit launched March 2026 listing die-to-memory (scale-in) as a first-order evaluation target
  • Disaggregated memory fabric architecture for post-HBM5 custom base die era
  Risks

  • Optical memory interconnect ships in product no earlier than after HBM5 — a long time axis
  • HBM4/HBM4E roadmap already locked in as copper/TSV extension
  • Memory latency must be won in tens of nanoseconds, a strict requirement
  • Investment is insurance, not a confirmed near-term production plan