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Research history/TSM

TSM

Taiwan Semiconductor Manufacturing Co Ltd

High Conviction

TSMC remains the clearest AI foundry and advanced-packaging bottleneck: Q1 2026 gross margin 66.25%, operating margin 58.1%, ROIC TTM 30.84%, forward P/E 21.36 and PEG 0.64 support a HIGH_CONVICTION view despite Taiwan and supply-chain tail risks.

Researched 23 days ago

High Conviction
Conviction75
Upside31
Risk-adj10
Holdbelow $338.40

TSMC remains the clearest AI foundry and advanced-packaging bottleneck: Q1 2026 gross margin 66.25%, operating margin 58.1%, ROIC TTM 30.84%, forward P/E 21.36 and PEG 0.64 support a HIGH_CONVICTION view despite Taiwan and supply-chain tail risks.

ScoresAnalyst DDAnalystSince lastRed flagsThesisConvictionQualityFinancialsValuationUpsideCycleCatalysts / RisksSizingRed-teamExpectationsFalsifiersSources

Recommendation

Hold

Quality holds but price is in the fair range — no action.

Recommendation

Hold

Conviction

75/100

high conviction

Upside

31/100

bull 70% · ~35% odds · +20% expected

Risk-adjusted upside

10/100

+10% after downside pressure

Thesis quality

8.9/10

Opportunity

5.4/10

Risk pressure

5.0/10

Valuation

Fair

AI fair value

$455.00

Fundamentals check

$357.03

12-24mo fair-value range

$360.00 / $455.00 / $525.00

width 36%

Buy below

$338.40

Trim above

$630.00

Implied expectations

achievable

29.1% implied revenue CAGR

Today's P/S implies ~29.1% revenue CAGR for five years versus 31.6% realized growth.

Analyst take (Substack DD)

  • damnangAgrees

    The SRAM-centric foundry-area thesis is consistent with TSMC's expanding margins and ROIC, but the packet does not quantify magnitude, so it supports optionality rather than base numbers.

  • damnangPartial

    The CoPoS roadmap supports the medium-term bottleneck thesis, but the post itself flags mass-production timing uncertainty and execution risk.

  • damnangPartial

    The glass-substrate and panel-level-packaging argument is strategically important, but yield, brittleness and substrate-choice uncertainty keep it out of the near-term base case.

  • damnangAgrees

    The Avicena optical-interconnect angle broadens TSMC's optical optionality, while commercialization remains too multi-year to drive current valuation alone.

  • damnangPartial

    The HBM base-die thesis is directionally favorable for TSMC, but the packet lacks a structured summary and quantified financial impact.

  • damnangPartial

    The Meta compute-misread post is useful narrative context for sector drawdowns, but it does not change TSMC's fundamental evidence in the packet.

Since Last Research

Material changes

  • Forward P/E moved to 21.36 from 21.86 and PEG to 0.64 from 0.66, modestly improving valuation support.
  • July recommendation mix improved to 13 strong buys and 28 buys versus 11 strong buys and 29 buys in June, supporting net-upgrade momentum.
  • New trusted Substack DD added SRAM/in-memory-compute, HBM base-die, CoPoS, glass substrate and optical-interconnect optionality.
  • Trusted X commentary added WF6 supply-chain disruption as a more explicit input risk.

Unchanged thesis elements

  • HIGH_CONVICTION verdict and 5-10% sizing band are unchanged.
  • Wide foundry and advanced-packaging moat remains the core thesis.
  • Direct exposure, pricing power and defensibility scores remain 9/9/9.
  • Taiwan geopolitical risk remains the largest structural red flag.

Red flags

  • Taiwan geopolitical concentration is a binary structural tail risk on leading-edge semiconductor capacity.
  • Trusted qualitative commentary flags WF6 supply-chain disruption risk tied to China export controls.
  • Valuation is richer than recent history on P/S and P/B, increasing multiple-compression risk.

AI-Infrastructure Thesis Fit

Foundry / advanced packagingOptical / CPO / silicon photonicsNetworking / custom ASICs / switching siliconAI accelerators / compute platform
Direct exposure9/10
Pricing power9/10
Defensibility9/10

TSMC is the central manufacturing bottleneck for leading-edge AI silicon and advanced packaging, with additional qualitative optionality from CoPoS, CPO and optical interconnect work.

Conviction Assessment

Moat

The moat is wide because leading-edge process scale, customer design lock-in and advanced packaging are difficult to replicate.

Bottleneck fit

TSMC directly controls constrained foundry and advanced-packaging capacity for AI accelerators and custom ASICs.

Valuation

Forward P/E of 21.36 and PEG of 0.64 are reasonable for expanding margins and 30.84% ROIC TTM.

Catalyst

H2 2026 COUPE/Xintec commentary and 2026 CoPoS pilot updates are thesis-relevant packaging catalysts.

Bull

  • AI accelerator demand keeps leading-edge utilization tight through 2027.
  • CoWoS, COUPE and CoPoS roadmaps extend TSMC's packaging bottleneck.
  • SRAM-centric inference and HBM base-die shifts increase foundry silicon area.

Bear

  • Taiwan geopolitical risk forces a persistent valuation discount.
  • AI capex growth slows and leading-edge pricing normalizes.
  • WF6 or other materials disruption pressures production continuity.

Business Quality

Description

TSMC is the dominant pure-play semiconductor foundry manufacturing leading-edge logic, AI accelerators, custom ASICs and advanced packages for global chip designers.

Value Chain

Infrastructure manufacturing layer: leading-edge foundry and advanced packaging between fabless chip designers and AI infrastructure builders.

Moat

wide

Scale, process leadership, customer design lock-in and advanced-packaging capacity create high switching costs for leading-edge AI silicon.

Pricing Power

high

Gross margin expanded to 66.25% in Q1 2026 while revenue per share rose, indicating pricing power in constrained leading-edge capacity.

Customer Concentration

Unavailable in the packet; major AI customers are not quantified as a percentage of revenue.

Financial Health

MetricValue
Revenue growth YoY35.13%
Gross margin66.25% ↑
Operating margin58.10%
FCF margin30.70%
Cash position—
Net debt / EBITDA—
Share count change YoY—
ROIC30.84%

Valuation

Forward P/E

21.36

Trailing P/E

23.66

PEG

0.64

EV/EBITDA

25.81

P/S

11.12

Sector: premiumHistory: above_average
PeerMetricValue
2303.TWpeer contextMature-node foundry peer; lacks TSMC's leading-edge and CoWoS bottleneck exposure.
2454.TWpeer contextFabless semiconductor peer and customer ecosystem participant, not a foundry-margin peer.
3711.TWpeer contextElectronics manufacturing and packaging-adjacent peer; lower direct leading-edge foundry exposure.

Upside Case

Bull fair value

$700.00

Probability

35%

Horizon

Long term

AI accelerator wafers compound through N2 and N3 rampsAdvanced packaging remains structurally scarceOptical and memory-on-logic optionality expands foundry area

Cycle Position

YTD

—

1Y

17.52%

Vs sector

—

From 52w high

-83.79%

Valuation: richerAnalysts: net_upgradesInsiders: net_buying

Catalysts & Risks

Near-term catalysts

  • Q2/Q3 2026 earnings cycle: watch whether gross margin remains above 60% and whether management confirms sustained leading-edge AI demand.
  • H2 2026 COUPE and Xintec-related advanced-packaging commentary: watch whether management or trusted channel checks confirm mass-production progress.

Medium-term catalysts

  • 2026 VisEra CoPoS pilot-line progress: watch whether TSMC confirms next-generation panel packaging stays on schedule.
  • 2027 CoPoS trial-production readout: watch whether panel-level packaging improves area utilization without yield slippage.
  • 2028-2029 CoPoS mass-production roadmap: watch whether Nvidia-related advanced-packaging demand converts into volume capacity.
RiskSeverityExplanation
Taiwan geopolitical concentrationhighLeading-edge capacity remains concentrated in Taiwan, creating a binary structural risk that can overwhelm company-specific execution.
Materials supply disruptionmediumTrusted commentary flags WF6 supply-chain stress from China export controls as a potential manufacturing input risk.
Valuation compressionmediumP/S of 11.12 and premium relative valuation leave the stock vulnerable if AI capex expectations slow or margins normalize.

Position Sizing

5%–10%

HIGH_CONVICTION quality and bottleneck fit justify the high-quality band, but Taiwan and valuation risks argue against exceeding the band.

Adversarial Review

Thesis blocked
Blocking concern: The HIGH_CONVICTION rests on a 'valuation attractive' condition that is circularly anchored to the current price and to peak-cycle 66% gross margins (vs 56% 5Y avg), so the claimed valuation edge is unproven and could invert into a double de-rating if margins normalize.

Strongest bear case

You are buying a cyclical foundry at a cyclical peak dressed up as a structural story. Gross margin is 66.25% in Q1 2026 versus a 56.31% 5-year average and 53.17% as recently as Q2 2024 — the entire earnings base sits ~10pts above trend, and EPS is up 58% YoY, the classic signature of peak-cycle. At the same time P/S TTM is 11.12 and EV/EBITDA TTM is 25.8 (versus 9.97 in 2022), both near the top of their own history. Demand is concentrated in a handful of AI hyperscalers (Nvidia named as taking most CoWoS), and the packet's own Substack flags the Meta compute-surplus reading already triggering semi sell-offs. A single quarter of AI-capex digestion normalizes margins toward 56% AND compresses the multiple simultaneously — a double de-rating on a name whose 'cheap' PEG of 0.64 silently assumes ~33% growth off record margins persists.

Challenges to the thesis

Load-bearing assumptionWhy it might be wrongSeverity
66.25% gross margin is structural pricing power, not cycle peak (gross_margin_trend: expanding).5Y average GM is 56.31% and Q2 2024 was 53.17%; the current 66% is a 10pt spread above trend. The report never argues why this reverts slowly, it just asserts duration. Normalizing to the 5Y mean cuts earnings power materially.high
PEG of 0.64 and forward P/E 21.36 make valuation attractive (a 'met' conviction condition).PEG 0.64 embeds ~33% sustained forward EPS growth computed off peak-margin earnings. If margins mean-revert, forward growth collapses and the PEG understates risk; forward P/E on peak EPS is a value trap, not a discount.high
AI accelerator demand keeps leading-edge utilization tight through 2027.This is an unquantified single-vector demand bet on hyperscaler capex; the packet's own damnang 'Meta compute-misread' post shows the market already selling semis on surplus fears. No customer-concentration figure is provided to bound the downside.high
CoPoS/COUPE/optical optionality justifies the +1 conviction bump.Every one of these is multi-year, pilot-stage, and the report's own analyst_take marks them PARTIAL with yield/timeline risk (mass production 2028-2030). Raising conviction on unquantified narrative optionality is circular.medium
Insider activity is net_buying and supportive.The transactions are tiny (94-17,835 shares) at a transactionPrice of 76.62 that matches neither the 411.03 quote nor the 1085-2535 TWD range — the signal is immaterial and the price field is internally inconsistent, so it should not count as confirmation.low

Missed / under-weighted red flags

  • Data-integrity break: current price 411.03 sits 84% below the 52-week low of 1085 and high of 2535 (yielding the nonsensical -83.79% from-high), indicating a USD-ADR vs TWD-financials unit mismatch that corrupts the valuation inputs.
  • Customer concentration marked 'Unavailable' and thus untreated as a risk — yet Nvidia is named as taking most CoWoS; a peer would carry an itemized concentration/demand-cliff risk, applied asymmetrically here.
  • All four FMP endpoints (income, balance sheet, cash flow, ratios) returned 403 — cash position and net-debt/EBITDA are 'unavailable' and financial health rests on a single unverified Finnhub source.
  • WF6 supply disruption from China export controls (25% of world supply) was rated TIER_A significance 6-7 BEARISH by the trusted handle but downgraded to 'medium' severity with no impact quantification.
  • EV/EBITDA TTM of 25.8 is near the top of its own 8-year range (9.97 in 2022) but is buried while the cheaper-looking forward P/E is foregrounded.
  • insider transactionPrice of 76.62 reconciles with no plausible TSM price, another unresolved packet inconsistency the primary pass presented as bullish confirmation.

Fair-value critique

The fair value is circular: the reasoning explicitly derives implied forward EPS FROM the current price and 21.36x forward P/E, then re-applies a 24x multiple — so $455 is just $411 × (24/21.36). It is not an independent anchor; it says only 'the stock is worth more if it trades at a higher multiple.' The multiple itself is a market price, and the embedded growth/margin assumptions (33% growth, 66% GM sustained) are the very things in dispute. The high case (525 at 27.5x, bull 700 at 35% prob) stacks multiple expansion on top of peak earnings with no DCF or normalized-margin cross-check; the range is anchored to consensus, not to intrinsic value.

Independent red-team pass · claude-opus-4-8 · 2026-07-16

Implied Expectations

plausible

What the price implies

  • At 21.36x forward P/E and 11.12x sales, the market already expects AI-driven growth and premium margins to persist.
  • The PEG of 0.64 implies forward earnings growth is still more than sufficient to justify the current earnings multiple if estimates hold.
  • Premium P/S and richer history-relative valuation imply little tolerance for a rapid normalization of gross margin below recent levels.

Our variant view

The market is underweighting the duration of TSMC's packaging and leading-edge foundry bottleneck; my fair value assumes margins stay structurally above prior-cycle norms longer than the current multiple implies.

Thesis Falsifiers

Pre-committed, dated checks that would disconfirm the thesis — a review is flagged automatically as each date passes.

If we observe…By…the thesis is wrong because
Gross margin falls below 55% for two consecutive reported quarters.2027-01-31Pricing-power thesis is weakened and the verdict should be downgraded to WATCH pending margin reset analysis.
Management or trusted channel checks indicate H2 2026 COUPE/Xintec mass-production progress is delayed beyond 2027.2027-02-28Advanced-packaging optionality is delayed and the fair-value multiple should compress.
CoPoS pilot-line progress is not confirmed during the 2026 reporting cycle.2026-12-31Medium-term packaging roadmap credibility falls and the thesis becomes less catalyst-backed.

Sources

ClaimSourceURLRetrieved
Company identity, exchange, industry, share count and market capitalization are from the company profile packet.finnhub:profile—retrieved 2026-07-16T13:36:58.288Z
Current price is 411.03 and market cap is 62,756,333.320312 in the profile currency units supplied by the packet.currentPrice—retrieved 2026-07-16T13:36:58.570Z
Q1 2026 sales per share was 43.7354 versus 32.3676 in Q1 2025, implying 35.13% YoY growth.finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-07-16T13:36:58.351Z
FY 2025 sales per share was 146.8919 versus 111.6216 in FY 2024, implying 31.6% YoY growth.finnhub:basic-financials—as of 2025-12-31 · retrieved 2026-07-16T13:36:58.351Z
Q1 2026 gross margin was 66.25%, operating margin was 58.1%, FCF margin was 30.7%, and ROIC TTM was 30.84%.finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-07-16T13:36:58.351Z
Gross margin expanded from 53.17% in Q2 2024 to 66.25% in Q1 2026 across the quarterly series.finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-07-16T13:36:58.351Z
Forward P/E was 21.36449, forward PEG was 0.6439, EV/EBITDA TTM was 25.8074, trailing P/E was 23.663 and P/S TTM was 11.1214.finnhub:basic-financials—as of 2026-03-31 · retrieved 2026-07-16T13:36:58.351Z
Annual P/S rose to 10.3484 in 2025 versus 9.6472 in 2024 and 7.1136 in 2023, supporting richer-than-history valuation.finnhub:basic-financials—as of 2025-12-31 · retrieved 2026-07-16T13:36:58.351Z
One-year price return was 17.51527% and the 52-week high was 2535 on 2026-06-23.finnhub:basic-financials—retrieved 2026-07-16T13:36:58.351Z
July 2026 analyst recommendations showed 13 strong buy, 28 buy, 2 hold and no sell ratings, up from 11 strong buy in June.finnhub:recommendations—as of 2026-07-01 · retrieved 2026-07-16T13:36:58.276Z
Recent insider transactions in the packet show multiple small purchase-coded transactions dated 2026-07-07.finnhub:insider-transactions—as of 2026-07-07 · retrieved 2026-07-16T13:36:58.296Z
Peers listed in the packet include 2454.TW, 3711.TW and 2303.TW.finnhub:peers—retrieved 2026-07-16T13:36:58.318Z
FMP income statement, balance sheet, cash flow and ratios endpoints returned 403 errors, so missing provider fields are marked unavailable.fmp:income-statement—retrieved 2026-07-16T13:36:58.527Z
FMP balance sheet endpoint returned 403, so cash position is unavailable rather than inferred.fmp:balance-sheet—retrieved 2026-07-16T13:36:58.531Z
FMP cash-flow endpoint returned 403, limiting direct cash-flow statement detail.fmp:cash-flow—retrieved 2026-07-16T13:36:58.519Z
FMP ratios endpoint returned 403, limiting cross-provider ratio verification.fmp:ratios—retrieved 2026-07-16T13:36:58.570Z
Trusted X commentary identified TSMC as a silicon photonics participant for CPO platforms.x:@aleabitoredditLinkas of 2026-07-13T19:20:46.000Z · retrieved 2026-07-16T13:36:58.104Z
Trusted X commentary flagged WF6 supply-chain disruption risk for TSMC from China export controls.x:@aleabitoredditLinkas of 2026-06-13T10:03:47.000Z · retrieved 2026-07-16T13:36:58.104Z
Trusted X commentary flagged TSMC COUPE mass production and Xintec-related CPO opportunity in H2 2026.x:@aleabitoredditLinkas of 2026-06-05T15:15:06.000Z · retrieved 2026-07-16T13:36:58.104Z
Trusted Substack DD argues SRAM-centric and in-memory-compute designs can shift more silicon area toward foundry manufacturing at TSMC.substack:damnangLinkas of 2026-07-01T07:55:52.000Z · retrieved 2026-07-16T13:36:58.103Z
Trusted Substack DD describes TSMC's CoPoS roadmap, 2026 pilot site, possible 2027 trial production and 2028-2029 mass-production path.substack:damnangLinkas of 2026-06-16T08:06:28.000Z · retrieved 2026-07-16T13:36:58.103Z
Trusted Substack DD frames glass and panel-level packaging as a multi-year CoPoS path with yield and qualification risk.substack:damnangLinkas of 2026-06-14T06:01:19.000Z · retrieved 2026-07-16T13:36:58.103Z
Trusted Substack DD describes TSMC's Avicena optical-interconnect positioning through CIS-process photodetector arrays.substack:damnangLinkas of 2026-06-04T08:01:25.000Z · retrieved 2026-07-16T13:36:58.103Z
Trusted Substack DD argues HBM base-die shifts can route more memory-related logic fabrication to TSMC.substack:damnangLinkas of 2026-07-09T10:12:07.000Z · retrieved 2026-07-16T13:36:58.103Z
Trusted Substack DD listed TSMC among semiconductor names affected by the Meta compute-surplus interpretation.substack:damnangLinkas of 2026-07-02T09:00:43.000Z · retrieved 2026-07-16T13:36:58.103Z

Analyst DD (Substack)

  • 6Substack · damnang·BULLISH / DEMAND·38 days agopost

    As SRAM-centric and in-memory-compute inference designs grow, memory is increasingly printed as logic silicon inside a foundry rather than bought as DRAM, shifting part of memory demand to the foundry. TSMC is the named manufacturer for Etched (N4P tapeout) and MatX.

    Evidence
    • Etched succeeded in its first silicon tapeout on TSMC's N4P process
    • MatX manufactures at TSMC
    • 'The more SRAM-centric design and in-memory compute grow, the more that volume flows to foundry silicon area rather than the DRAM of the three memory makers'
    • Nvidia takes most CoWoS (advanced packaging) capacity
    Catalysts
    • Etched first racks shipping summer 2026
    • Growth of SRAM-centric and digital in-memory compute designs
    Risks
    • Low-cost DRAM camp (d-Matrix organic substrate, Tenstorrent GDDR) deliberately routes around CoWoS packaging capacity
    • Thematic claim; magnitude of the DRAM-to-foundry shift is not quantified
  • 6Substack · damnang·NEUTRAL / EXECUTION·53 days agopost

    TSMC is developing CoPoS (Chip on Panel on Substrate) as the next step beyond CoWoS, using square panels instead of round wafers to fit ever-larger AI accelerator chips with less edge waste. The direction is clear but both glass's structural role and the mass-production timeline remain undecided, with the chairman warning there are no shortcuts.

    Evidence
    • First panel format is 310mm x 310mm, with a cited roadmap growing through 515mm x 510mm up to 750mm x 620mm
    • A round 12-inch wafer yields only four to seven large packages per sheet, which a square panel improves on
    • Pilot line laid down at TSMC subsidiary VisEra in 2026; press accounts cite small trial production in 2027 and mass production in 2028-2029
    • Chairman C.C. Wei stated mass production takes another two to three years with no shortcuts; some on the ground see 2029-2030
    • Mass-production site is the fourth phase of the AP7 campus in Chiayi, Taiwan, with NVIDIA cited as first customer
    • TSMC validated a 0.8-millimeter glass core substrate with Ibiden and Innolux under a program named 'glass substrate for CoWoS', while saying mass production is still far off
    Catalysts
    • VisEra pilot line in 2026
    • Trial production cited for 2027
    Risks
    • Whether glass enters as interposer or core substrate is unfixed, and which path reaches mass production first is open
    • Thin glass interposer (~400 micrometers) makes CTE management tricky and warpage worsens as the panel grows, repeatedly cited as the biggest barrier
    • Timeline weighted toward slipping, possibly to 2029-2030
    • Intel and Samsung are pushing competing panel packaging and glass approaches
  • 6Substack · damnang·NEUTRAL / EXECUTION·55 days agopost

    AI accelerator packages have outgrown organic substrates and the lithography reticle limit, forcing a shift to larger square panels (panel-level packaging) and glass materials. TSMC's CoPoS (Chip-on-Panel-on-Substrate) is the vehicle for this transition, with glass currently most solidly positioned on the temporary carrier side and a pilot line on schedule to finish within the year.

    Evidence
    • TSMC's current CoWoS binds an NVIDIA GPU and HBM into one package using a silicon interposer
    • Reticle limit is ~26 x 33mm (~858 sq mm); AI accelerators crossed it long ago and stitch multiple dies together
    • TSMC's package area roadmap moves from 5.5x the reticle to 9.5x then 14x; 9.5x is roughly 8,000 sq mm (~9cm per side)
    • Per Ming-Chi Kuo's June industry check, CoPoS uses a 310 x 310mm glass carrier, with a 510 x 515mm glass panel processed into a glass core substrate floated at the volume stage
    • TSMC is moving on schedule to finish the pilot line for next-generation panel packaging within the year
    Catalysts
    • Completion of the CoPoS pilot line within the year
    • Transition to panel-level packaging (PLP) raising area utilization above 75 percent
    Risks
    • Glass replacement of the silicon interposer classified by Taiwanese industry press as a long-term task
    • Core substrate adoption for CoPoS is closer to industry check and estimate than confirmation; what substrate early volume runs use remains open
    • Glass is brittle, making yield and customer qualification the central hurdle
  • 6Substack · damnang·BULLISH / EXECUTION·65 days agopost

    TSMC is positioning across optical interconnect technologies, partnering with Avicena (April 2025) to use its CMOS image sensor processes for photodetector arrays and investing through VentureTech Alliance. This is a foundry's hedge against silicon photonics CPO, leveraging an existing high-volume CIS ecosystem.

    Evidence
    • April 2025 collaboration to use TSMC CIS processes to optimize and mass-produce LightBundle photodetector arrays
    • VentureTech Alliance (TSMC's VC arm) joined Avicena's May 2025 $65M Series B
    • Silicon PD arrays are already mass-produced by the CIS industry at scale of hundreds of millions of pixels
    • Described as a foundry's hedge: not going all-in on silicon photonics CPO while keeping a foot on MicroLED
    Catalysts
    • PD array mass-production collaboration repurposing existing CIS portfolio
    • MicroLED-based CPO market projected by TrendForce to form in 2028, reaching $850M by 2030
    Risks
    • MicroLED interconnect commercialization path is multi-year and unproven at scale
    • Fiber bundle and packaging cited as the likely production bottleneck
    • Proprietary architecture with no standards ecosystem